Simulation run order

Each timestep runs three phases, repeated until time > stop. Knowing the order explains most of the language's restrictions — why state is digital-only, and why V() always returns the previous solve.

Phase A — execute logic

Three domain passes, in fixed causal order:

1. module — structural logic runs first. Wire signals are read from the previous MNA solution via V() and I() and made available to downstream domains.
2. digital — digital logic runs second. state variables are updated, if/while blocks are evaluated, and control outputs are written to their signal names.
3. analog — analog device models run last. Node voltages from the previous solve and control signals from the digital pass are read to compute device currents and physics outputs.

Phase B — stamp logic outputs into MNA

Every driven voltage_source and current_source reads its controlling signal from the values written in Phase A and updates the MNA right-hand side vector b.

Phase C — solve and advance

The linear system G · x = b is solved — or iterated to convergence, for implicit solvers. Node voltages and branch currents are committed, the signals listed in .save are recorded, and time advances by dt.

Then it repeats, until time > stop.

Why the order is fixed

The ordering within Phase A holds regardless of declaration order in the source file. A digital controller will always see the structural V() reads from the current step, and an analog device model will always see the digital control output from the current step — so causality doesn't depend on how you happened to arrange the file.

It also explains the two rules that catch people out:

• V() and I() read the previous solve, because Phase A runs before Phase C has produced a new one. See Built-in intrinsics.
• state is legal in digital but not analog, because digital runs once per accepted timestep while analog is re-entered on every Newton-Raphson iteration inside Phase C. See Why two computational domains.